Load Cache

As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the eeects of memory access latency. In this paper, we introduce a novel modiication of the processor pipeline called memory renaming. Memory renaming applies register access techniques to load instructions, reducing the eeect of delays caused by the need to calculate effective addresses for the load and all preceding stores before the data can be fetched. Memory renaming allows the processor to speculatively fetch values when the producer of the data can be reliably determined without the need for an eeective address. This work extends previous studies of data value and dependence speculation. When memory renaming is added to the processor pipeline, renaming can be applied to 30% to 50% of all memory references, translating to an overall improvement in execution time of up to 41%. Furthermore, this improvement is seen across all memory segments { including the heap segment which has often been diicult to manage eeciently.